Digitally Controlled Oscillator for mm-Wave Frequencies

In the fifth generation of mobile communication, 5G, frequencies above 30 GHz, so-called millimeter-wave (mm-wave) frequencies are expected to play a prominent role. For the synthesis of these frequencies, the all-digital phase locked loop (ADPLL) has recently gained much attention. A core component of the ADPLL is the digitally controlled oscillator (DCO), an oscillator that tunes the frequency discretely. For good performance, the frequency steps must be made very small, while the total tuning range must be large. This thesis covers several coarse- and fine-tuning techniques for DCOs operating at mm-wave frequencies. Three previously not published fine-tuning schemes are presented: The first one tunes the second harmonic, which will, due to the Groszkowski effect, tune the fundamental tone. The second one is a current-modulation scheme, which utilizes the weak current-dependence of the capacitance of a transistor to tune the frequency. In the third one, a digital-to-analog converter (DAC) is connected to the bulk of the differential pair and tunes the frequency by setting the bulk voltage. The advantages and disadvantages of the presented tuning schemes are discussed and compared with previously reported fine-tuning schemes. Two oscillators were implemented at 86 GHz. Both oscillator use the same oscillator core and hence have the same power consumption and tuning range, 14.1 mW and 13.9%. A phase noise of -89.7 dBc/Hz and -111.4 dBc/Hz at 1 MHz and 10 MHz offset, respectively, were achieved, corresponding to a Figure-of-Merit of -178.5 dBc/Hz. The first oscillator is fine-tuned using a combination of a transformer-based fine-tuning and the current modulation scheme presented here. The achieved frequency resolution is 55 kHz, but can easily be made finer. The second oscillator utilizes the bulk bias technique to achieve its fine tuning. The fine-tuning resolution is here dependent on the resolution of the DAC; a 100μV resolution corresponds to a resolution of 50 kHz.n 2011, the global monthly mobile data usage was 0.5 exabytes, or 500 million gigabytes. In 2016, this number had increased to 7 exabytes, an increase by a factor 14 in just five years, and there are no signs of this trend slowing down. To meet the demands of the ever increasing data usage, engineers have begun to investigate the possibility to use significantly higher frequencies, 30 GHz or higher, for mobile communication than what is used today, which is 3 GHz or below. To be able to transmit and receive data at these high frequency, an oscillator capable of operating at these frequencies are required. An oscillator is an electrical circuit that generates an alternating current (a current that first goes one way, and then the other) at a specific frequency. Below is an example to illustrate to function and importance of the oscillator: Imagine driving a car and listening to the radio. Suddenly, a horrendous song starts playing from the radio, so you instantly tune to another station and find some great, smooth jazz. Satisfied, you lean back and drive on. But what exactly happened when you "tuned to another station"? What you really did was changing the frequency of the oscillator, which can be found in the radio receiver of the car. The radio receiver filters out all frequencies, except for the frequency of the local oscillator. So by setting the frequency of the local oscillator to the frequency of the desired radio channel, only this radio channel will reach the speakers of the car. Thus, the oscillator must be able to vary its frequency to any frequency that a radio station can transmit on. While an old car radio may seem like a simple example, the very same principle is used in mobile communication, even at frequencies above 30 GHz. The oscillator is also used in the same way when transmitting signals, so that the signals are transmitted on the correct frequency. The design of the local oscillator is a hot topic among radio engineers. A poorly designed oscillator will ruin the performance of the whole receiver or transmitter. This thesis covers the design of a special type of oscillators, called digital controlled oscillators or DCO, operating at 30 GHz or higher. The frequency of these oscillators are determined by a digital word (ones and zeros), instead of using an analog voltage, which is traditionally used. Digital control results in greater flexibility and higher noise-resilience, but it also means that the frequency can’t be changed continuously, but rather in discrete steps. This discrete behavior will cause noise in the receiver. To minimize this noise, the frequency steps should be minimized. In this thesis, we have proposed a DCO design, operating at 85.5 GHz, which can be tuned almost 7 % in either direction. To our knowledge, no other DCO operates at such high frequencies. In the proposed oscillators the frequency steps are only 55 kHz apart, which is so small that its effect on the radio receiver can, with a good conscience, be ignored. This is achieved with a novel technique that makes tiny, tiny changes in the current that passes through the oscillator

Ring amplifiers for high speed pipeline assisted SAR ADCs

This thesis contains a review of published ring amplifier topologies. It is suggested to split the input stage of the ring amplifier into two. In this way, a robust ring amplifier can be designed without stacking the transistors in the second stage of the ring amplifier, boosting its speed properties. The split input stage can also be used to design a fully differential bias enhanced ring amplifier, boosting the ring amplifiers settling properties at the cost of lower gain. A figure of merit for the ring amplifiers is suggested. The advantages and disadvantages of using ring amplifiers in pipeline assisted SAR ADC is discussed with regards to noise power, linearity, settling speed and PVT robustness. A figure of merit for ring amplifiers is suggested. A ring amplifier based pipeline assisted SAR ADC is implemented with some non-critical components realized using behavioral modelling. The implemented ADC reaches, SNR 58 dB, SFDR 71 dB, consuming 3.3 mW operating at 550 MHz. The performance of the pipelined SAR ADC is compared with an existing conventional SAR ADC. It is concluded that the ring amplifier is well suited for high speed pipeline assisted SAR ADCs from a noise, linearity and power perspective but it is somewhat limited by its relatively low settling speed.Popular scientific summary: Ring amplifiers for high speed pipeline assisted SAR ADCs During the two last decades the digital infrastructure has expanded enormously. This has been enabled by the very fast development of transistor technology, where the size of the transistors has decreased exponentially. Often summarized as Moore’s law. This has led to new possibilities of processing data in the digital domain, but also lead to increased strain on the interfaces between the digital and analog world. One of these interfaces is the Analog to digital converters (ADC). Digital circuits almost always benefit from smaller transistors. For analog circuits is not so simple, some analog circuit does even deteriorate when the transistor becomes increasingly smaller. This has led to a push, where it is attempted to design analog circuits and architectures with as many digital components as possibly. One such architecture is the successive approximation ADC (SAR ADC). The SAR ADC preforms binary search on the input voltage. While the SAR ADC is very friendly to small transistors and have low power consumption. The SAR ADC is characterized by low conversion speed and is somewhat limited by noise, injected by the transistors preforming the conversion. One way of approach this is to split the SAR ADC into the pipeline SAR ADC, figure (b) below. This does however require a residue amplifier, stuffed in between the two ADC in figure (b). Unfortunately, the traditionally used residue amplifier consumes a large part of the total power consumption of the whole ADC. This have sparked a search for novel residue amplifier that are friendly to small transistors. The thesis is concerned with studying one such amplifier namely the ring amplifier. Ring amplifier is built with inverters, one of the most important design blocks in digital designs. The thesis concludes that ring amplifier have high potential for high speed pipeline SAR ADC. In terms of linearity noise and power consumption but are somewhat limited by low settling speed